The introduction of high-k and metal gate materials in scaled CMOS technologies (45 nm node and beyond) faces significant difficulties due to severe threshold voltage instability and performance degradation of the devices. These problems are related to the high amount of bulk defects and interface states in the high-k/metal gate stack. In addition, preferential lateral re-oxidation of the gate dielectric is a significant problem, especially for short channel devices. Proper passivation of the dielectric is crucial in order to overcome these problems.
Passivation of Hf based high-k dielectric materials by Fluorine as possible means to reduce the number of interface and bulk defects is an attractive alternative to H passivation, and was the subject of several recent studies. The reason for this is that Hf and Si bonds formed with F are much stronger compared to Hf—H and Si—H bonds. The strength of the formed bonds allows the passivation to be maintained even throughout the standard high temperature CMOS processing for deep submicron devices, and results in a more robust defect passivation that allows better withstanding of the normal device operation conditions, resulting in improved BTI behavior.
The conventional method for Fluorine introduction is by means of implantation techniques. However, several implantations during the gate stack deposition are needed in order to passivate the entire dielectric. The incorporation of Fluorine in an HfO2 comprising high-k stack using implantation techniques is described by Seo et al (IEDM Technical Digest, p. 647-650, 2005). However, implanting Fluorine during the gate stack deposition may lead to uncontrolled oxide re-growth as described by Mogul et al (IEEE Trans. Electron Dev., pp. 388-394, 1997).
As a conclusion there is still a need to find a more attractive method to achieve Fluorine incorporation (passivation) in the high-k dielectric material.